View 9DB1904BKLF_5181941.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

9db1904b idt ? 19 output differential buffer for pcie gen2 and qpi 1607c ?04/19/11 19 output differential buffer for pcie gen2 and qpi 1 datasheet description the 9db1904 is electrically compatible to the intel db1900gs differential buffer specification. this buffer provides 19 output clocks for pci-express gen2 or intel qpi 6.4gt/s applications. a differential clock from a ck410b+ main clock generator, such as the ics932s421 drives the 9db1904 . the 9db1904 can provide outputs up to 400mhz in bypass mode. key specifications ? dif output cycle-to-cycle jitter < 50ps ? dif output-to-output skew < 150ps across all outputs features/benefits ? power up default is all outputs in 1:1 mode/no smbus programming ? spread spectrum compatible/emi reductions ? supports output frequencies up to 400 mhz in bypass mode/flexible fanout buffer ? 8 selectable smbus addresses/no smbus segmentation required ? smbus address determines pll or bypass mode/pin savings ? dedicated vdda and ckpwrgd_pd# pins/easy board design pin configuration recommended application 19 output differential buffer for pcie gen2 and qpi smb_a2_pllbyp# clk_in# clk_in oe17_18# dif_18# dif_18 dif_17# dif_17 gnd vdd dif_16# dif_ 16 oe15_16# dif_15# dif_15 ckpwrgd_pd# dif_14# dif_14 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 iref 1 54 oe14# gnda 2 53 dif_13# vdda 3 52 dif_13 high_bw# 4 51 oe13# 100m_133m#_lv 5 50 dif_12# dif_0 6 49 dif_12 dif_0# 7 48 oe12# dif_1 8 47 vdd dif_1# 9 46 gnd gnd 10 45 dif_11# vdd 11 44 dif_11 dif_2 12 43 oe11# dif_2# 13 42 dif_10# dif_3 14 41 dif_10 dif_3# 15 40 oe10# dif_4 16 39 dif_9# dif_4# 17 38 dif_9 oe_01234# 18 37 oe9# 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 smbclk smbdat oe5# dif_5 dif_5# oe6# dif_6 dif_6# vdd gnd oe7# dif_7 dif_7# oe8# dif_8 dif_8# smb_a0 smb_a1 9DB1904BKLF functionality at power up (pll mode) 100m_133m# clk_in mhz dif_(18:0) mhz 1 100mhz clk_in 0 133mhz clk_in power down functionality outputs ckpwrgd_ pd# clk_in/ clk_in# dif/dif# 1 runnin g runnin g on 0x hi-z off pll state inputs
idt ? 19 output differential buffer for pcie gen2 and qpi 1607c ?04/19/11 9db1904b 19 output differential buffer for pcie gen2 and qpi 2 pin description pin # pin name pin type description 1 iref out this pin establishes the reference for the differential current-mode output pairs. it requires a fixed precision resistor to ground. 475ohm is the standard value for 100ohm differential impedance. other impedances require different values. see data sheet. 2 gnda pwr ground pin for the pll core. 3 vdda pwr 3.3v power for the pll core. 4high_bw# in 3.3v input for selecting pll band width 0 = high, 1= low 5 100m_133m#_lv in low threshold input to select operating frequency. see functionality table for definition 6 dif_0 out 0.7v differential true clock output 7 dif_0# out 0.7v differential complementary clock output 8 dif_1 out 0.7v differential true clock output 9 dif_1# out 0.7v differential complementary clock output 10 gnd pwr ground pin. 11 vdd pwr power supply, nominal 3.3v 12 dif_2 out 0.7v differential true clock output 13 dif_2# out 0.7v differential complementary clock output 14 dif_3 out 0.7v differential true clock output 15 dif_3# out 0.7v differential complementary clock output 16 dif_4 out 0.7v differential true clock output 17 dif_4# out 0.7v differential complementary clock output 18 oe_01234# in active low input for enabling dif pairs 0, 1, 2, 3 and 4. 1 =disable outputs, 0 = enable outputs 19 smbclk in clock pin of smbus circuitr y , 5v tolerant 20 smbdat i/o data pin of smbus circuitry, 5v tolerant 21 oe5# in active low input for enabling dif pair 5. 1 =disable outputs, 0 = enable outputs 22 dif_5 out 0.7v differential true clock output 23 dif_5# out 0.7v differential complementary clock output 24 oe6# in active low input for enabling dif pair 6. 1 =disable outputs, 0 = enable outputs 25 dif_6 out 0.7v differential true clock output 26 dif_6# out 0.7v differential complementary clock output 27 vdd pwr power supply, nominal 3.3v 28 gnd pwr ground pin. 29 oe7# in active low input for enabling dif pair 7. 1 =disable outputs, 0 = enable outputs 30 dif_7 out 0.7v differential true clock output 31 dif_7# out 0.7v differential complementary clock output 32 oe8# in active low input for enabling dif pair 8. 1 =disable outputs, 0 = enable outputs 33 dif_8 out 0.7v differential true clock output 34 dif_8# out 0.7v differential complementary clock output 35 smb_a0 in smbus address bit 0 (lsb) 36 smb_a1 in smbus address bit 1
idt ? 19 output differential buffer for pcie gen2 and qpi 1607c ?04/19/11 9db1904b 19 output differential buffer for pcie gen2 and qpi 3 pin description (continued) pin # pin name pin type description 37 oe9# in active low input for enabling dif pair 9. 1 =disable outputs, 0 = enable outputs 38 dif_9 out 0.7v differential true clock output 39 dif_9# out 0.7v differential complementary clock output 40 oe10# in active low input for enabling dif pair 10. 1 =disable outputs, 0 = enable outputs 41 dif_10 out 0.7v differential true clock output 42 dif_10# out 0.7v differential complementary clock output 43 oe11# in active low input for enabling dif pair 11. 1 =disable outputs, 0 = enable outputs 44 dif_11 out 0.7v differential true clock output 45 dif_11# out 0.7v differential complementary clock output 46 gnd pwr ground pin. 47 vdd pwr power supply, nominal 3.3v 48 oe12# in active low input for enabling dif pair 12. 1 =disable outputs, 0 = enable outputs 49 dif_12 out 0.7v differential true clock output 50 dif_12# out 0.7v differential complementary clock output 51 oe13# in active low input for enabling dif pair 13. 1 =disable outputs, 0 = enable outputs 52 dif_13 out 0.7v differential true clock output 53 dif_13# out 0.7v differential complementary clock output 54 oe14# in active low input for enabling dif pair 14. 1 =disable outputs, 0 = enable outputs 55 dif_14 out 0.7v differential true clock output 56 dif_14# out 0.7v differential complementary clock output 57 ckpwrgd_pd# in 3.3v input notifies device to sample latched inputs and start up on first high assertion, or exit power down mode on subsequent assertions. low enters power down mode. 58 dif_15 out 0.7v differential true clock output 59 dif_15# out 0.7v differential complementary clock output 60 oe15_16# in active low input for enabling dif pairs 15 and 16. 1 =disable outputs, 0 = enable outputs 61 dif_ 16 out 0.7v differential true clock output 62 dif_16# out 0.7v differential complementary clock output 63 vdd pwr power supply, nominal 3.3v 64 gnd pwr ground pin. 65 dif_17 out 0.7v differential true clock output 66 dif_17# out 0.7v differential complementary clock output 67 dif_18 out 0.7v differential true clock output 68 dif_18# out 0.7v differential complementary clock output 69 oe17_18# in active low input for enabling dif pairs 17 and 18. 1 =disable outputs, 0 = enable outputs 70 clk_in in true input for differential reference clock. 71 clk_in# in complementary input for differential reference clock. 72 smb_a2_pllbyp# in smbus address bit 2. when low, the part operates as a fanout buffer with the pll bypassed. when high, the part operates as a zero-delay buffer (zdb) with the pll operating. 0 = fanout mode (pll bypassed), 1 = zdb mode (pll used)
idt ? 19 output differential buffer for pcie gen2 and qpi 1607c ?04/19/11 9db1904b 19 output differential buffer for pcie gen2 and qpi 4 functional block diagram power groups clk_in clk_in# dif(18:0) high_bw# smb_a2_pllbyp# smbdat smbclk ckpwrgd_pd# 19 iref oe(17_18)# oe(15_16)# oe(14:5)#, oe_01234# 13 smb_a0 smb_a1 100m_133m#_lv pll (ss compatible) logic vdd gnd 3 2 pll, analog 11,27,47,63 10,28,46,64 dif clocks description pin number byte 9, bit 2 100m_133m#_lv byte9, bit 1 fsb byte 9, bit 0 fsa clk_in mhz dif outputs mhz notes 1 0 1 100.00 100.00 1 0 0 1 133.33 133.33 2 notes:fs_a_410 = 1 1. powerup default for 100m_133m# = 1 2. powerup default for 100m_133m# = 0 9db1904 frequency selects for pll mode
idt ? 19 output differential buffer for pcie gen2 and qpi 1607c ?04/19/11 9db1904b 19 output differential buffer for pcie gen2 and qpi 5 electrical characteristics - absolute maximum ratings parameter symbol conditions min typ max units notes 3.3v core supply voltage vdda 4.6 v 1,2 3.3v logic supply voltage vdd 4.6 v 1,2 input low voltage v il gnd-0.5 v 1 input high voltage v ih except for smbus interface v dd +0.5v v 1 input high voltage v ihsmb smbus clock and data pins 5.5v v 1 storage temperature ts -65 150 c 1 junction temperature tj 125 c 1 input esd protection esd prot human body model 2000 v 1 1 guaranteed b y desi g n and characterization, not 100% tested in production. 2 operation under these conditions is neither implied nor g uaranteed. electrical characteristics - clock input parameters ta = t com; supply voltage vdd/vdda = 3.3 v +/-5%, see test loads for loading conditions parameter symbol conditions min typ max units notes input high voltage - dif_in v i hdi f differential inputs (single-ended measurement) 600 800 1150 mv 1 input low voltage - dif_in v ildif differential inputs (single-ended measurement) v ss - 300 0 300 mv 1 input common mode voltage - dif_in v com common mode input voltage 300 1000 mv 1 input amplitude - dif_in v swing peak to peak value 300 1450 mv 1 input slew rate - dif_in dv/dt measured differentially 0.4 8 v/ns 1,2 input leakage current i in v in = v dd , v in = gnd -5 5 ua 1 input duty cycle d tin measurement from differential wavefrom 45 55 % 1, 3 input jitter - cycle to cycle j di fi n differential measurement 0 125 ps 1 1 guaranteed b y desi g n and characterization, not 100% tested in production. 2 slew rate measured throu g h +/-75mv window centered around differential zero 3 input dut y c y cle will directl y impact output dut y c y cle in b y pass mode. it has no impact in pll mode. electrical characteristics - current consumption ta = t com; supply voltage vdd/vdda = 3.3 v +/-5%, see test loads for loading conditions parameter symbol conditions min typ max units notes i dd3. 3op vdd, all outputs active @100mhz 425 450 ma 1 i dd3. 3aop vdda, all outputs active @100mhz 35 45 ma 1 i dd3. 3pd vdd 20 25 ma 1 i dd3.3apd vdda 12 15 ma 1 1 guaranteed by design and characterization, not 100% tested in production. zo = 100 ? powerdown current operating supply current
idt ? 19 output differential buffer for pcie gen2 and qpi 1607c ?04/19/11 9db1904b 19 output differential buffer for pcie gen2 and qpi 6 electrical characteristics - input/supply/common parameters ta = t com; supply voltage vdd/vdda = 3.3 v +/-5%, see test loads for loading conditions parameter symbol conditions min typ max units notes ambient operating temperature t com commmercial range 0 70 c 1 input high voltage v ih single-ended inputs, except smbus, low threshold and tri-level inputs 2v dd + 0.3 v 1 input low voltage v il single-ended inputs, except smbus, low threshold and tri-level inputs gnd - 0.3 0.8 v 1 low threshold input- high voltage v ih_fs 3.3 v +/-5%, applies to 100m_133m#_lv pin 0.7 v dd + 0.3 v 1 low threshold input- low voltage v il_fs 3.3 v +/-5%, applies to 100m_133m#_lv pin v ss - 0.3 0.35 v 1 i in single-ended inputs, v in = gnd, v in = vdd -5 5 ua 1 i inp single-ended inputs v in = 0 v; inputs with internal pull-up resistors v in = vdd; inputs with internal pull-down resistors -200 200 ua 1 f ib yp v dd = 3.3 v, bypass mode 33 400 mhz 2 f i p ll v dd = 3.3 v, 100mhz pll mode 90 100.00 110 mhz 2 f i p ll v dd = 3.3 v, 133.33mhz pll mode 120 133.33 147 mhz 2 pin inductance l p in 7nh1 c in logic inputs, except dif_in 1.5 5 pf 1 c i ndi f_i n dif_in differential clock inputs 1.5 2.7 pf 1,4 c out output pin capacitance 6 pf 1 clk stabilization t stab from v dd power-up and after input clock stabilization or de-assertion of pd# to 1st clock 1.8 ms 1,2 input ss modulation frequency f modi n allowable frequency (triangular modulation) 30 33 khz 1 oe# latency t latoe# dif start after oe# assertion dif stop after oe# deassertion 412clocks1,3 tdrive_pd# t drvpd dif output enable after pd# de-assertion 300 us 1,3 tfall t f fall time of control inputs 5 ns 1,2 trise t r rise time of control inputs 5 ns 1,2 smbus input low voltage v ilsmb 0.8 v 1 smbus input high voltage v ihsmb 2.1 v ddsmb v1 smbus output low voltage v olsmb @ i pullup 0.4 v 1 smbus sink current i pullup @ v ol 4ma1 nominal bus voltage v ddsmb 3v to 5v +/- 10% 2.7 5.5 v 1 sclk/sdata rise time t rsmb (max vil - 0.15) to (min vih + 0.15) 1000 ns 1 sclk/sdata fall time t fsmb (min vih + 0.15) to (max vil - 0.15) 300 ns 1 smbus operating frequency f maxsmb maximum smbus operating frequency 100 khz 1,5 1 guaranteed by design and characterization, not 100% tested in production. 2 control input must be monotonic from 20% to 80% of input swing. 5 the differential in p ut clock must be runnin g for the smbus to be active input current 3 time from deassertion until out p uts are >200 mv 4 dif_in input capacitance input frequency
idt ? 19 output differential buffer for pcie gen2 and qpi 1607c ?04/19/11 9db1904b 19 output differential buffer for pcie gen2 and qpi 7 differential zo rp rp hscl output buffer 9dbxxx differential test loads rs rs 2pf 2pf differential output termination table dif zo ( ? )iref ( ? )rs ( ? )rp ( ? ) 100 475 33 50 85 412 27 43.2 electrical characteristics - dif 0.7v current mode differential outputs ta = t com; supply voltage vdd/vdda = 3.3 v +/-5%, see test loads for loading conditions parameter symbol conditions min typ max units notes slew rate trf scope avera g in g on 1 2 4 v/ns 1, 2, 3 slew rate matching trf slew rate matching, scope averaging on 12.6 20 % 1, 2, 4 voltage high vhigh 660 797 850 1 voltage low vlow -150 39 150 1 max voltage vmax 857 1150 1 min volta g evmin -3007 1 vswin g vswin g scope avera g in g off 300 1510 mv 1, 2 crossin g volta g e (abs) vcross_abs scope avera g in g off 250 378 550 mv 1, 5 crossing voltage (var) -vcross scope averaging off 57 140 mv 1, 6 2 measured from differential waveform 6 the total variation of all vcross measurements in any particular system. note that this is a subset of v_cross_min/max (v_cros s absolute) allowed. the intent is to limit vcross induced modulation by setting v_cross_delta to be smaller than v_cross absolut e. mv statistical measurement on single-ended signal using oscillosc ope math function. (scope averaging on) measurement on single ended signal using absolute value. (scope avera g in g off) mv 1 guaranteed by design and characterization, not 100% tested in production. iref = vdd/(3xr r ). for r r = 475 ? (1%), i ref = 2.32ma. i oh = 6 x i ref and v oh = 0.7v @ z o =50 ? (100 ? differential impedance). 3 slew rate is measured through the vswing voltage range centered around differential 0v. this results in a +/-150mv window arou nd differential 0v. 4 matching applies to rising edge rate of clock / falling edge rate of clock#. it is measured in a +/-75mv window centered on the average cross point where clock rising meets clock# fa lling. the median cross point is used to calculate the voltage thresholds the oscilloscope uses for the edge rate calculations. 5 vcross is defined as voltage where clock = clock# measured on a component test board and only applies to the differential risi ng edge (i.e. clock rising and clock# falling).
idt ? 19 output differential buffer for pcie gen2 and qpi 1607c ?04/19/11 9db1904b 19 output differential buffer for pcie gen2 and qpi 8 electrical characteristics - output duty cycle, jitter, skew and pll characterisitics ta = t com; supply voltage vdd = 3.3 v +/-5% parameter symbol conditions min typ max units notes -3db point in high bw mode 2 3 4 mhz 1 -3db point in low bw mode 0.7 1 1.4 mhz 1 pll jitter peaking t jpeak peak pass band gain 1.4 2 db 1 duty cycle t dc measured differentially, pll mode 45 49.5 55 % 1,2 duty cycle distortion t dcd measured differentially, bypass mode @100mhz -2 1 2 % 1,2,5 t pdbyp bypass mode, nominal value @ 25c, 3.3v, v t = 50% 2500 3700 4500 ps 1,2,4 t pdpll pll mode, nominal value @ 25c, 3.3v, v t = 50% 100 300 500 ps 1,2,3 dif_in, dif [x:0] t pd_byp input-to-output skew variation in bypass mode (over specified voltage / temperature operating ranges) |500| |600| ps 1,2,4,6,7, 8,9,13 dif_in, dif [x:0] t pd_pll input-to-output skew variation in pll mode (over specified voltage / temperature operating ranges) |250| |350| ps 1,2,3,6,7, 8,9,13 dif[x:0] t jph differential phase jitter (rms value) 2 10 ps 1,7,10 dif[x:0] t ssterror differential spread spectrum tracking error (p eak to p eak ) 40 80 ps 1,7,12 skew, output to output t sk3 v t = 50% 100 150 ps 1 pll mode 40 50 ps 1,2 additive jitter in bypass mode 25 50 ps 1,2 1 guaranteed by design and characterization, not 100% tested in production. c loa d = 2pf 5 duty cycle distortion is the difference in duty cycle between the output and the input clock when the device is operated in by pass mode. 6 vt = 50% of vout 11 t is the period of the input clock jitter, cycle to cycle 7 this parameter is deterministic for a given device 8 measured with scope averaging on to find mean value. 9 long-term variation from nominal of input-to-output skew over temperature and voltage for a single device. 10 this parameter is measured at the outputs of two separate 9db1904 devices driven by a single main clock. the 9db1904's must be set to high bandwidth. differential phase jitter is the accumulation of the phase jitter not shared by the outputs (eg. not including the affects of spread spectrum). target ranges of consideration are agents with bw of 1-22mhz and 11-33mhz. 12 differential spread spectrum tracking error is the difference in spread spectrum tracking between two 9db1904 devices this parameter is measured at the outputs of two separate 9db1904 devices driven by a single main clock in spread spectrum mode. the 9db1904's must be set to high bandwidth. the spread spectrum characteristics are: maximum of 0.5%, 30-33khz modulation frequency, linear profile. pll bandwidth bw skew, input to output 13 this parameter is an absolute value. it is not a double-sided figure. t jcyc-cyc 2 measured from differential cross-point to differential cross-point 3 pll mode input-to-output skew is measured at the first output edge following the corresponding input. 4 all bypass mode input-to-output specs refer to the timing between an input edge and the specific output edge created by it.
idt ? 19 output differential buffer for pcie gen2 and qpi 1607c ?04/19/11 9db1904b 19 output differential buffer for pcie gen2 and qpi 9 electrical characteristics - phase jitter parameters ta = t com; supply voltage vdd/vdda = 3.3 v +/-5%, see test loads for loading conditions parameter symbol conditions min typ max units notes t jp hpcieg1 pcie gen 1 35 86 ps (p-p) 1,2,3 pcie gen 2 lo band 10khz < f < 1.5mhz 1.2 3 ps (rms) 1,2 pcie gen 2 high band 1.5mhz < f < nyquist (50mhz) 2.5 3.1 ps (rms) 1,2 t jphqpi_smi qpi & smi (100mhz or 133mhz, 4.8gb/s, 6.4gb/s 12ui) 0.30 0.5 ps (rms) 1,5 t jphpcieg1 pcie gen 1 3 10 ps (p-p) 1,2,3 pcie gen 2 lo band 10khz < f < 1.5mhz 0.01 0.3 ps (rms) 1,2,6 pcie gen 2 high band 1.5mhz < f < nyquist (50mhz) 0.8 1.3 ps (rms) 1,2,6 t jphqpi_smi qpi & smi (100mhz or 133mhz, 4.8gb/s, 6.4gb/s 12ui) 0.12 0.3 ps (rms) 1,5,6 1 applies to all outputs. 6 for rms figures, additive jitter is calculated by solving the following equation: (additive jitter)^2 = (total jittter)^2 - (i nput jitter)^2 5 calculated from intel-supplied clock jitter tool v 1.6.3 t jphpcieg2 t jphpcieg2 2 see http://www.pcisig.com for complete specs 3 sample size of at least 100k cycles. this figures extrapolates to 108ps pk-pk @ 1m cycles for a ber of 1-12. 4 subject to final radification by pci sig. phase jitter, pll mode additive phase jitter, bypass mode clock periods - differential outputs with spread spectrum disabled 1 clock 1us 0.1s 0.1s 0.1s 1us 1 clock -c2c jitter absper min -ssc short-term average min - ppm long-term average min 0 ppm period nominal + ppm long-term average max +ssc short-term average max +c2c jitter absper max 100.00 9.94900 9.99900 10.00000 10.00100 10.05100 ns 1,2 133.33 7.44925 7.49925 7.50000 7.50075 7.55075 ns 1,2 clock periods - differential outputs with spread spectrum enabled 1 clock 1us 0.1s 0.1s 0.1s 1us 1 clock -c2c jitter absper min -ssc short-term average min - ppm long-term average min 0 ppm period nominal + ppm long-term average max +ssc short-term average max +c2c jitter absper max 99.75 9.94906 9.99906 10.02406 10.02506 10.02607 10.05107 10.10107 ns 1,2 133.00 7.44930 7.49930 7.51805 7.51880 7.51955 7.53830 7.58830 ns 1,2 1 guaranteed by desi g n and characterization, not 100% tested in production. dif dif notes 2 all long term accuracy specifications are guaranteed with the assumption that the input clock complies with ck410b+/ck420bq accuracy requirements. the 9db1904 itself does not contribute to ppm error. measurement window units ssc on center freq. mhz notes measurement window units ssc off center freq. mhz
idt ? 19 output differential buffer for pcie gen2 and qpi 1607c ?04/19/11 9db1904b 19 output differential buffer for pcie gen2 and qpi 10 common recommendations for differential routing dimension or value unit figure l1 length, route as non-coupled 50ohm trace 0.5 max inch 1 l2 length, route as non-coupled 50ohm trace 0.2 max inch 1 l3 length, route as non-coupled 50ohm trace 0.2 max inch 1 rs 33 ohm 1 rt 49.9 ohm 1 down device differential routing l4 length, route as coupled microstrip 100ohm differential trace 2 min to 16 max inch 1 l4 length, route as coupled stripline 100ohm differential trace 1.8 min to 14.4 max inch 1 differential routing to pci express connector l4 length, route as coupled microstrip 100ohm differential trace 0.25 to 14 max inch 2 l4 length, route as coupled stripline 100ohm differential trace 0.225 min to 12.6 max inch 2 dif reference clock hcsl output buffer l1 l1' rs l2 l2' rs l4' l4 l3 l3' rt rt pci express down device ref_clk input figure 1: down device routing hcsl output buffer l1 l1' rs l2 l2' rs l4' l4 l3 l3' rt rt pci express add-in board ref_clk input figure 2: pci express connector routing
idt ? 19 output differential buffer for pcie gen2 and qpi 1607c ?04/19/11 9db1904b 19 output differential buffer for pcie gen2 and qpi 11 vdiff vp-p vcm r1 r2 r3 r4 note 0.45v 0.22v 1.08 33 150 100 100 0.58 0.28 0.6 33 78.7 137 100 0.80 0.40 0.6 33 78.7 none 100 ics874003i-02 input compatible 0.60 0.3 1.2 33 174 140 100 standard lvds r1a = r1b = r1 r2a = r2b = r2 alternative termination for lvds and other common differential signals (figure 3) hcsl output buffer l1 l1' r1b l2 l2' r1a l4' l4 l3 r2a r2b down device ref_clk input figure 3 l3' r3 r4 component value note r5a, r5b 8.2k 5% r6a, r6b 1k 5% cc 0.1 f vcm 0.350 volts cable connected ac coupled application (figure 4) pcie device ref_clk input figure 4 r5a l4' l4 3.3 volts r5b r6a r6b cc cc
idt ? 19 output differential buffer for pcie gen2 and qpi 1607c ?04/19/11 9db1904b 19 output differential buffer for pcie gen2 and qpi 12 9db1904 smbus address mapping when using ck410/ck410b, 9fg1200, and 9db403/803 smb adr: dc 9db403/803 (db400/800) smb adr: d2 932s421 ck410b pll bypass mode smb_a2_pllbyp# = 0 pll zdb mode smb_a2_pllbyp# = 1 smb_a(2:0) = 100 smb adr: d8 smb_a(2:0) = 101 smb adr: da smb_a(2:0) = 110 smb adr: dc smb_a(2:0) = 111 smb adr: de smb_a(2:0) = 000 smb adr: d0 9db1904 smb_a(2:0) = 001 smb adr: d2 smb_a(2:0) = 010 smb adr: d4 smb_a(2:0) = 011 smb adr: d6 9db1904 9db1904 9db1904 9db1904 9db1904 9db1904 9db1904 smb_a(2:0) = 100 smb adr: d8 9fg1201 (db1200g) smb_a(2:0) = 101 smb adr: da 9fg1201 (db1200g) smb_a(2:0) = 110 smb adr: dc 9fg1201 (db1200g) smb_a(2:0) = 111 smb adr: de 9fg1201 (db1200g) smb_a(2:0) = 000 smb adr: d0 9fg1201 (db1200g) smb_a(2:0) = 001 smb adr: d2 9fg1201 (db1200g) smb_a(2:0) = 010 smb adr: d4 9fg1201 (db1200g) smb_a(2:0) = 011 smb adr: d6 9fg1201 (db1200g) or or or or or or or or or or
idt ? 19 output differential buffer for pcie gen2 and qpi 1607c ?04/19/11 9db1904b 19 output differential buffer for pcie gen2 and qpi 13 general smbus serial interface information for the 9db1904b how to write: ? controller (host) sends a start bit. ? controller (host) sends the write address d4 (h) ? idt clock will acknowledge ? controller (host) sends the begining byte location = n ? idt clock will acknowledge ? controller (host) sends the data byte count = x ? idt clock will acknowledge ? controller (host) starts sending byte n through byte n + x -1 ? idt clock will acknowledge each byte one at a time ? controller (host) sends a stop bit how to read: ? controller (host) will send start bit. ? controller (host) sends the write address d4 (h) ? idt clock will acknowledge ? controller (host) sends the begining byte location = n ? idt clock will acknowledge ? controller (host) will send a separate start bit. ? controller (host) sends the read address d5 (h) ? idt clock will acknowledge ? idt clock will send the data byte count = x ? idt clock sends byte n + x -1 ? idt clock sends byte 0 through byte x (if x (h) was written to byte 8) . ? controller (host) will need to acknowledge each byte ? controllor (host) will send a not acknowledge bit ? controller (host) will send a stop bit t start bit wr write rt repeat start rd read beginning byte n byte n + x - 1 n not acknowledge pstop bit idt (slave/receiver) controller (host) x byte ack ack data byte count = x ack slave address d5 (h) * index block read operation slave address d4 (h) * beginning byte = n ack ack idt (slave/receiver) t wr ack ack ack ack ack pstop bit x byte index block write operation slave address d4 (h) * beginning byte = n write start bit controller (host) byte n + x - 1 data byte count = x beginning byte n
idt ? 19 output differential buffer for pcie gen2 and qpi 1607c ?04/19/11 9db1904b 19 output differential buffer for pcie gen2 and qpi 14 smbustable: reserved register pin # name control function t yp e0 1pwd bit 7 r 1 bit 6 r 1 bit 5 r 1 bit 4 r 1 bit 3 r 1 bit 2 r 0 bit 1 r 1 bit 0 r 1 smbustable: output control register pin # name control function t yp e0 1pwd bit 7 dif_7 output control rw hi-z enable 1 bit 6 dif_6 output control rw hi-z enable 1 bit 5 dif_5 output control rw hi-z enable 1 bit 4 dif_4 output control rw hi-z enable 1 bit 3 dif_3 output control rw hi-z enable 1 bit 2 dif_2 output control rw hi-z enable 1 bit 1 dif_1 output control rw hi-z enable 1 bit 0 dif_0 output control rw hi-z enable 1 smbustable: output and pll bw control register pin # name control function t yp e0 1pwd bit 7 rw hi g h b w low b w 1 bit 6 rw b y pass pll 1 bit 5 dif_13 output control rw hi-z enable 1 bit 4 dif_12 output control rw hi-z enable 1 bit 3 dif_11 output control rw hi-z enable 1 bit 2 dif_10 output control rw hi-z enable 1 bit 1 dif_9 output control rw hi-z enable 1 bit 0 dif_8 output control rw hi-z enable 1 note: bit 7 is wired or to the high_bw# input, any 0 selects high bw note: bit 6 is wired or to the smb_a2_pllbyp# input, any 0 selects fanout bypass mode smbustable: output enable readback register pin # name control function t yp e0 1pwd bit 7 r x bit 6 r x bit 5 r x bit 4 r x bit 3 r x bit 2 r x bit 1 r x bit 0 r x 72 see note pll_bw# ad j ust see note bypass# test mode / pll b y te 3 8 b y te 1 - - - - b y te 0 - - reserved - - reserved reserved reserved readback - oe9# input readback - oe8# input readback readback readback - oe7# input readback readback - oe_01234# input readback readback - oe5# input readback - oe6# input readback readback readback - smb_a2_pll byp# in readback readback - high_bw# in readback b y te 2 reserved reserved reserved reserved
idt ? 19 output differential buffer for pcie gen2 and qpi 1607c ?04/19/11 9db1904b 19 output differential buffer for pcie gen2 and qpi 15 smbustable: output enable readback register pin # name control function t yp e0 1pwd bit 7 r x bit 6 r x bit 5 0 bit 4 r x bit 3 r x bit 2 r x bit 1 r x bit 0 r x smbustable: vendor & revision id register pin # name control function t yp e0 1pwd bit 7 rid3 r - - 0 bit 6 rid2 r - - 0 bit 5 rid1 r - - 0 bit 4 rid0 r - - 1 bit 3 vid3 r - - 0 bit 2 vid2 r - - 0 bit 1 vid1 r - - 0 bit 0 vid0 r - - 1 smbustable: device id (194 decimal or c2 hex) pin # name control function t yp e0 1pwd bit 7 rw 1 bit 6 rw 1 bit 5 rw 0 bit 4 rw 0 bit 3 rw 0 bit 2 rw 0 bit 1 rw 1 bit 0 rw 0 smbustable: byte count register pin # name control function t yp e0 1pwd bit 7 bc7 rw - - 0 bit 6 bc6 rw - - 0 bit 5 bc5 rw - - 0 bit 4 bc4 rw - - 0 bit 3 bc3 rw - - 0 bit 2 bc2 rw - - 1 bit 1 bc1 rw - - 1 bit 0 bc0 rw - - 1 - - - 54 51 48 43 - - - - - reserved readback readback readback reserved readback reserved reserved reserved device id 1 reserved writing to this register configures how many bytes will be read back. - - - 60 - - 40 - - device id 3 device id 4 readback - oe12# input vendor id readback - oe11# input device id 5 device id 6 device id 7 (msb) - b y te 5 - b y te 6 69 - reserved device id 2 b y te 4 b y te 7 - - - - - - reserved revision id readback readback - oe10# input readback - oe14# input readback readback - oe13# input readback - oe15_16# input readback - oe17_18# input readback reserved device id 0
idt ? 19 output differential buffer for pcie gen2 and qpi 1607c ?04/19/11 9db1904b 19 output differential buffer for pcie gen2 and qpi 16 smbustable: control pin readback register pin # name control function t yp e0 1pwd bit 7 r latch bit 6 x bit 5 x bit 4 dif_18 output control rw hi-z enable 1 bit 3 dif_17 output control rw hi-z enable 1 bit 2 dif_16 output control rw hi-z enable 1 bit 1 dif_15 output control rw hi-z enable 1 bit 0 dif_14 output control rw hi-z enable 1 smbustable: pll operating set point register pin # name control function t yp e0 1pwd bit 7 0 bit 6 0 bit 5 0 bit 4 0 bit 3 0 bit 2 rw latch bit 1 rw 0 bit 0 rw 1 reserved reserved frequency select 100m_133m# frequenc y select b frequenc y select a see ics9db1904 1:1 pll programming table reserved 5 b y te 8 - - - reserved b y te 9 readback -100m_133m#_lv reserved readback reserved reserved
idt ? 19 output differential buffer for pcie gen2 and qpi 1607c ?04/19/11 9db1904b 19 output differential buffer for pcie gen2 and qpi 17 e top view or anvil singulation a3 l n (ref.) e e e e (ref. ) (ref. ) (ref. ) (typ.) if a1 even e2 d2 d2 2 a c 0.08 c e2 2 2 2 1 sawn singulation index area seating plane are even thermal base odd b (n - 1)x n 1 chamfer 4x 0.6 x 0.6 max optional d d & & n d n d n e n e & n d n e (n - 1)x e dimensions a0.81.0 n 72 a1 0 0.05 n d 18 a3 n e 18 b 0.18 0.3 d x e basic 10.00 x 10.00 e d2 min. / max. 5.75 / 6.15 e2 min. / max. 5.75 / 6.15 l min. / max. 0.30/ 0.50 ics 72l tolerance thermally enhanced, very thin, fine pitch quad flat / no lead plastic package symbol min. max. symbol 0.25 reference 0.50 basic ordering information part / order number shipping packaging package temperature 9DB1904BKLF tubes 72-pin mlf 0 to +70 c 9DB1904BKLFt tape and reel 72-pin mlf 0 to +70 c "lf" suffix to the part number are the pb-free configuration, rohs compliant. "b" is the device revision designator (will not correlate with the datasheet revision).
9db1904b 19 output differential buffer for pcie gen2 and qpi 18 innovate with idt and accelerate your future networks. contact: www.idt.com for sales 800-345-7015 408-284-8200 fax: 408-284-2775 for tech support 408-284-6578 pcclockhelp@idt.com corporate headquarters integrated device technology, inc. 6024 silver creek valley road san jose, ca 95138 united states 800 345 7015 +408 284 8200 (outside u.s.) asia pacific and japan idt singapore pte. ltd. 1 kallang sector #07-01/06 kolamayer industrial park singapore 349276 phone: 65-6-744-3356 fax: 65-6-744-1764 europe idt europe limited 321 kingston road leatherhead, surrey kt22 7tu england phone: 44-1372-363339 fax: 44-1372-378851 ? 2011 integrated device technology, inc. all rights reserved. product specifications subject to change without notice. idt and the idt logo are trademarks of integrated device technology, inc. accelerated thinking is a service mark of integrated device technology, inc. all other brand s, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. printed in usa revision history rev. issue date description page # 0.1 7/1/2009 initial release - 0.2 7/8/2009 updated revision id in byte 5 13 a 9/21/2010 updated electrical characteristics tables. added test loads and terminations corrected minor t y po's, move to release. various b 9/23/2010 1. updated electrical char tables 2. updated test loads and termination figures 3. added period ppm tables various c 4/19/2011 1. updated electrical tabels with typ. values 2. updated differential clock period ppm tables various

▲Up To Search▲

Price & Availability of 9DB1904BKLF

	To Download 9DB1904BKLF Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .